AT91FR40162SCJ

Product Summary

The AT91FR40162SCJ is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor of the AT91FR40162SCJ has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. The AT91FR40162SCJ ARM microcontroller features 2 Mbits of on-chip SRAM and 2 Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of integration and very small footprint make the device ideal for space-constrained applications. The high-speed on-chip SRAM of the AT91FR40162SCJ enables a performance of up to 74 MIPs in typical conditions with significant power reduction and EMC improvement over an external SRAM implementation. The Flash memory may be programmed via the JTAG/ICE interface or the factoryprogrammed Flash Memory Uploader (FMU) using a single device supply, making the AT91FR40162SCJ suitable for in-system programmable applications.

Parametrics

AT91FR40162SCJ absolute maximum ratings: (1)Operating Temperature (Industrial) . -40℃ to + 85℃; (2)Storage Temperature: -60℃ to + 150℃; (3)Voltage on Any Input Pin with Respect to Ground: -0.3V to max of VDDIO; + 0.3V and 3.6V; (4)Maximum Operating Voltage (VDDIO): 3.6V; (5)Maximum Operating Voltage (VDDCORE): 1.95V; (6)Voltage on VPP with Respect to Ground: -0.6V to +13.0V.

Features

AT91FR40162SCJ features: (1)Incorporates the ARM7TDMI ARM Thumb Processor Core: High-performance 32-bit RISC Architecture; High-density 16-bit Instruction Set; Leader in MIPS/Watt; EmbeddedICE(In-circuit Emulation); (2)256K Bytes of On-chip SRAM: 32-bit Data Bus, Single-clock Cycle Access; (3)1024K Words 16-bit Flash Memory (2M bytes): Single Voltage Read/Write; Sector Erase Architecture; Erase Suspend Capability; Low-power Operation; Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection; Reset Input for Device Initialization; Sector Program Unlock Command; 128-bit Protection Register; factory-programmed AT91 Flash Memory Uploader Software; (4)Fully Programmable External Bus Interface (EBI): Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes; Software Programmable 8/16-bit External Data Bus; (5)8-level Priority, Individually Maskable, Vectored Interrupt Controller: 4 External Interrupts, Including a High-priority Low-latency Interrupt Request; (6)32 Programmable I/O Lines: 3-channel 16-bit Timer/Counter; (7)3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel; (8)2 USARTs: Two Dedicated Peripheral Data Controller (PDC) Channels per USART.

Diagrams